Exploiting don't cares to enhance functional tests
نویسندگان
چکیده
I n simulation based design verification, deterministic or pseudo-random tests are used to check functional correctness of a design. I n this paper we present a technique generating tests by specifying the don’t care inputs in the functional specifications so as to improve their coverage of both design errors and manufacturing faults. The don’t cares are chosen to maximize sensitization of signals in the circuit. The tests generated in this way requzre only a fraction ofpseudo-exhaustive test patterns to achieve a high multiplicity of fault coverage.
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